High-Level Synthesis for Highly-Efficient Accelerators Enabling Post-Silicon Engineering Change

With the rising cost of SoC development and the shorter time-to-market, the demand for postsilicon programmability has been increasing. Recently, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However, programmable accelerators suffer from low energy efficiency mainly due to their extensive use of memories. This paper first proposes highly-efficient programmable accelerators which enable post-silicon engineering change. The proposed accelerators acheive high efficiency by implementing the controllers mostly by hard-wired logic and providing a control patching mechanism. Then, we propose a patch compilation technique from a given set of an original design and a modified design. Experimental results demonstrate that the proposed accelerators can acheive higher energy efficiency than the existing programmable accelerators.